| Series | DSPLL® |
| Package | Tray |
| Part Status | Active |
| Type | Clock Jitter Attenuator |
| PLL | Yes with Bypass |
| Input | Clock, Crystal |
| Output | CML, LVCMOS, LVDS, LVPECL |
| Number of Circuits | 1 |
| Ratio - Input:Output | 3:1 |
| Differential - Input:Output | Yes/Yes |
| Frequency - Max | 710MHz |
| Divider/Multiplier | Yes/No |
| Voltage - Supply | 1.71V ~ 3.63V |
| Operating Temperature | -40°C ~ 85°C |
| Mounting Type | Surface Mount |
| Package / Case | 36-VFQFN Exposed Pad |
| Supplier Device Package | 36-QFN (6x6) |
